/*
* codrv_mcan.h
*
* Copyright (c) 2012-2019 emotas embedded communication GmbH
*-------------------------------------------------------------------
* SVN  $Id: codrv_mcan.h 51556 2023-12-18 09:35:01Z ro $
*
*
*-------------------------------------------------------------------
*
*
*/


/********************************************************************/
/**
* \file
* \brief mcan from BOSCH (e.g. STM32H7,lpc546xx)
*
*/

#ifndef CODRV_MCAN_H
#define CODRV_MCAN_H 1


#define MCAN_CCCR_BIT_INIT	(1ul << 0u)
#define MCAN_CCCR_BIT_CCE	(1ul << 1u)
#define MCAN_CCCR_BIT_ASM	(1ul << 2u)
#define MCAN_CCCR_BIT_CSA	(1ul << 3u)
#define MCAN_CCCR_BIT_CSR	(1ul << 4u)
#define MCAN_CCCR_BIT_MON	(1ul << 5u)
#define MCAN_CCCR_BIT_DAR	(1ul << 6u)
#define MCAN_CCCR_BIT_TEST	(1ul << 7u)
#define MCAN_CCCR_BIT_FDOE	(1ul << 8u)
#define MCAN_CCCR_BIT_BRSE	(1ul << 9u)
#define MCAN_CCCR_BIT_NISO	(1ul << 15u)

#define MCAN_IE_BIT_RF0NE	(1ul << 0u)
#if defined(CODRV_MCAN_STM32_L5) || defined(CODRV_MCAN_STM32_G0) || defined(CODRV_MCAN_STM32_G4) || defined(CODRV_MCAN_STM32_U5) || defined(CODRV_MCAN_STM32_H5)
#define MCAN_IE_BIT_TCE		(1ul << 7u)
#define MCAN_IE_BIT_EP		(1ul << 17u)
#define MCAN_IE_BIT_BO		(1ul << 19u)
#else /* defined(CODRV_MCAN_STM32_L5) || defined(CODRV_MCAN_STM32_G0) || defined(CODRV_MCAN_STM32_G4) || defined(CODRV_MCAN_STM32_U5) || defined(CODRV_MCAN_STM32_H5) */
#define MCAN_IE_BIT_TCE		(1ul << 9u)
#define MCAN_IE_BIT_EP		(1ul << 23u)
#define MCAN_IE_BIT_BO		(1ul << 25u)
#endif /* defined(CODRV_MCAN_STM32_L5) || defined(CODRV_MCAN_STM32_G0) || defined(CODRV_MCAN_STM32_G4) || defined(CODRV_MCAN_STM32_U5) || defined(CODRV_MCAN_STM32_H5) */

#define MCAN_PSR_BIT_EP		(1ul << 5u)
#define MCAN_PSR_BIT_EW		(1ul << 6u)
#define MCAN_PSR_BIT_BO		(1ul << 7u)

#define MCAN_CANID_BIT_XTD	(1ul << 30u)
#define MCAN_CANID_BIT_RTR	(1ul << 29u)


#if defined(CODRV_MCAN_STM32_MP1)
typedef struct
{
   UNSIGNED32              CREL;                 /*!< CAN master control register,         							Address offset: 0x000          */
   UNSIGNED32              ENDN;                 /*!< CAN master status register,          							Address offset: 0x004          */
   UNSIGNED32              RESERVED0;            /*!< reserved					        							Address offset: 0x008          */
   UNSIGNED32              DBTP;                 /*!< CAN Data bit timing and prescaler,							Address offset: 0x00C          */
   UNSIGNED32              TEST;                 /*!< CAN Test register,         									Address offset: 0x010          */
   UNSIGNED32              RWD;                  /*!< CAN interrupt enable register,       							Address offset: 0x014          */
   UNSIGNED32              CCCR;                 /*!< CAN CC control,           									Address offset: 0x018          */
   UNSIGNED32              NBTP;                 /*!< CAN Nominal bit timing and prescaler,							Address offset: 0x01C          */
   UNSIGNED32              TSCC;                 /*!< CAN Timestamp counter configuration,  						Address offset: 0x020          */
   UNSIGNED32              TSCV;                 /*!< CAN Timestamp counter value,          						Address offset: 0x024          */
   UNSIGNED32              TOCC;                 /*!< CAN Timeout counter configuration,    						Address offset: 0x028          */
   UNSIGNED32              TOCV;                 /*!< CAN Timeout counter value,         							Address offset: 0x02C          */
   UNSIGNED32              RESERVED1[4];         /*!< reserved,         											Address offset: 0x030          */
   UNSIGNED32              ECR;                  /*!< CAN Error counter,       										Address offset: 0x040          */
   UNSIGNED32              PSR;                  /*!< CAN Protocol status,           								Address offset: 0x044          */
   UNSIGNED32              TDCR;                 /*!< CAN Transmitter delay compensator,    						Address offset: 0x048          */
   UNSIGNED32              RESERVED2;            /*!< reserved,         											Address offset: 0x04C          */
   UNSIGNED32              IR;                   /*!< CAN Interrupt,          										Address offset: 0x050          */
   UNSIGNED32              IE;                   /*!< CAN Interrupt enable,        									Address offset: 0x054          */
   UNSIGNED32              ILS;                  /*!< CAN Interrupt line select,         							Address offset: 0x058          */
   UNSIGNED32              ILE;                  /*!< CAN Interrupt line enable,         							Address offset: 0x05C          */
   UNSIGNED32              RESERVED3[8];         /*!< reserved,       												Address offset: 0x060          */
   UNSIGNED32              GFC;                  /*!< CAN Global filter configuration,      						Address offset: 0x080          */
   UNSIGNED32              SIDFC;                /*!< CAN standard ID filter configuration,							Address offset: 0x084          */
   UNSIGNED32              XIDFC;                /*!< CAN extended ID filter configuration,		  					Address offset: 0x088          */
   UNSIGNED32              RESERVED4;            /*!< reserved,       												Address offset: 0x08C          */
   UNSIGNED32              XIDAM;                /*!< CAN Extended ID and mask,        								Address offset: 0x090          */
   UNSIGNED32              HPMS;                 /*!< CAN High priority message status,         					Address offset: 0x094          */
   UNSIGNED32              NDAT1;                /*!< new data 1,       											Address offset: 0x098          */
   UNSIGNED32              NDAT2;                /*!< new data 2,       											Address offset: 0x09C          */
   UNSIGNED32              RXF0C;                /*!< CAN Rx FIFO 0 configuration,           						Address offset: 0x0A0          */
   UNSIGNED32              RXF0S;                /*!< CAN Rx FIFO 0 status,             							Address offset: 0x0A4          */
   UNSIGNED32              RXF0A;                /*!< CAN Rx FIFO 0 acknowledge,         							Address offset: 0x0A8          */
   UNSIGNED32              RXBC;                 /*!< CAN Rx buffer configuration,          						Address offset: 0x0AC          */
   UNSIGNED32              RXF1C;                /*!< CAN Rx FIFO 1 configuration,        							Address offset: 0x0B0          */
   UNSIGNED32              RXF1S;                /*!< CAN Rx FIFO 1 status,         								Address offset: 0x0B4          */
   UNSIGNED32              RXF1A;                /*!< CAN Rx FIFO 1 acknowledge,         							Address offset: 0x0B8          */
   UNSIGNED32              RXESC;                /*!< CAN Rx buffer and FIFO element size configuration,       		Address offset: 0x0BC          */
   UNSIGNED32              TXBC;                 /*!< CAN Tx buffer configuration,           						Address offset: 0x0C0          */
   UNSIGNED32              TXFQS;                /*!< CAN Tx FIFO/queue status,             						Address offset: 0x0C4          */
   UNSIGNED32              TXESC;                /*!< CAN Tx buffer element size configuration,         			Address offset: 0x0C8          */
   UNSIGNED32              TXBRP;                /*!< CAN Tx buffer request pending,          						Address offset: 0x0CC          */
   UNSIGNED32              TXBAR;                /*!< CAN Tx buffer add request,        							Address offset: 0x0D0          */
   UNSIGNED32              TXBCR;                /*!< CAN Tx buffer cancellation request,         					Address offset: 0x0D4          */
   UNSIGNED32              TXBTO;                /*!< CAN Tx buffer transmission occurred,         					Address offset: 0x0D8          */
   UNSIGNED32              TXBCF;                /*!< CAN Tx buffer cancellation finished,       					Address offset: 0x0DC          */
   UNSIGNED32              TXBTIE;               /*!< CAN Tx buffer transmission interrupt enable,           		Address offset: 0x0E0          */
   UNSIGNED32              TXBCIE;               /*!< CAN Tx buffer cancellation finished interrupt enable,         Address offset: 0x0E4          */
   UNSIGNED32              RESERVED5[2];         /*!< reserved,         											Address offset: 0x0E8          */
   UNSIGNED32              TXEFC;                /*!< CAN Tx event FIFO configuration,          					Address offset: 0x0F0          */
   UNSIGNED32              TXEFS;                /*!< CAN Tx event FIFO status,        								Address offset: 0x0F4          */
   UNSIGNED32              TXEFA;                /*!< CAN Tx event FIFO acknowledge,         						Address offset: 0x0F8          */
   UNSIGNED32              RESERVED6;            /*!< reserved,														Address offset: 0x0FC          */
   UNSIGNED32              TTTMC;                /*!< CAN TT trigger memory configuration,         					Address offset: 0x100          */
   UNSIGNED32              TTRMC;                /*!< CAN TT reference message configuration,         				Address offset: 0x104          */
   UNSIGNED32              TTOCF;                /*!< CAN TT operation configuration,         						Address offset: 0x108          */
   UNSIGNED32              TTMLM;                /*!< CAN TT matrix limits register,         						Address offset: 0x10C          */
   UNSIGNED32              TURCF;                /*!< CAN TUR configuration,         								Address offset: 0x110          */
   UNSIGNED32              TTOCN;                /*!< CAN TT operation control,         							Address offset: 0x114          */
   UNSIGNED32              TTGTP;                /*!< CAN TT global time preset,         							Address offset: 0x118          */
   UNSIGNED32              TTTMK;                /*!< CAN TT time mark,         									Address offset: 0x11C          */
   UNSIGNED32              TTIR;                 /*!< CAN TT interrupt,         									Address offset: 0x120          */
   UNSIGNED32              TTIE;                 /*!< CAN TT interrupt enable,         								Address offset: 0x124          */
   UNSIGNED32              TTILS;                /*!< CAN TT interrupt line select,         						Address offset: 0x128          */
   UNSIGNED32              TTOST;                /*!< CAN TT operation status,         								Address offset: 0x12C          */
   UNSIGNED32              TURNA;                /*!< CAN TUR numerator actual,         							Address offset: 0x130          */
   UNSIGNED32              TTLGT;                /*!< CAN TT local and global time,         						Address offset: 0x134          */
   UNSIGNED32              TTCTC;                /*!< CAN TT cycle time and count,         							Address offset: 0x138          */
   UNSIGNED32              TTCPT;                /*!< CAN TT capture time,         									Address offset: 0x13C          */
   UNSIGNED32              TTCSM;                /*!< CAN TT cycle sync mark,         								Address offset: 0x140          */
   UNSIGNED32              RESERVED7[111];       /*!< reserved,         											Address offset: 0x144          */
   UNSIGNED32              TTTS;                 /*!< CAN TT trigger select,										Address offset: 0x300          */
} CODRV_MCANFD_T;

#else /* defined(CODRV_MCAN_STM32_MP1) */

# if defined(CODRV_MCAN_STM32_L5) || defined(CODRV_MCAN_STM32_G0) || defined(CODRV_MCAN_STM32_G4) || defined(CODRV_MCAN_STM32_U5) || defined(CODRV_MCAN_STM32_H5)

typedef struct
{
   UNSIGNED32              CREL;                 /*!< CAN master control register,         							Address offset: 0x00          */
   UNSIGNED32              ENDN;                 /*!< CAN master status register,          							Address offset: 0x04          */
   UNSIGNED32              CUST;                 /*!< CAN transmit status register,        							Address offset: 0x08          */
   UNSIGNED32              DBTP;                 /*!< CAN Data bit timing and prescaler,							Address offset: 0x0C          */
   UNSIGNED32              TEST;                 /*!< CAN Test register,         									Address offset: 0x10          */
   UNSIGNED32              RWD;                  /*!< CAN interrupt enable register,       							Address offset: 0x14          */
   UNSIGNED32              CCCR;                 /*!< CAN CC control,           									Address offset: 0x18          */
   UNSIGNED32              NBTP;                 /*!< CAN Nominal bit timing and prescaler,							Address offset: 0x1C          */
   UNSIGNED32              TSCC;                 /*!< CAN Timestamp counter configuration,  						Address offset: 0x20          */
   UNSIGNED32              TSCV;                 /*!< CAN Timestamp counter value,          						Address offset: 0x24          */
   UNSIGNED32              TOCC;                 /*!< CAN Timeout counter configuration,    						Address offset: 0x28          */
   UNSIGNED32              TOCV;                 /*!< CAN Timeout counter value,         							Address offset: 0x2C          */
   UNSIGNED32              RESERVED0[4];         /*!< reserved,         											Address offset: 0x30          */
   UNSIGNED32              ECR;                  /*!< CAN Error counter,       										Address offset: 0x40          */
   UNSIGNED32              PSR;                  /*!< CAN Protocol status,           								Address offset: 0x44          */
   UNSIGNED32              TDCR;                 /*!< CAN Transmitter delay compensator,    						Address offset: 0x48          */
   UNSIGNED32              RESERVED1;            /*!< reserved,         											Address offset: 0x4C          */
   UNSIGNED32              IR;                   /*!< CAN Interrupt,          										Address offset: 0x50          */
   UNSIGNED32              IE;                   /*!< CAN Interrupt enable,        									Address offset: 0x54          */
   UNSIGNED32              ILS;                  /*!< CAN Interrupt line select,         							Address offset: 0x58          */
   UNSIGNED32              ILE;                  /*!< CAN Interrupt line enable,         							Address offset: 0x5C          */
   UNSIGNED32              RESERVED2[8];         /*!< reserved,       												Address offset: 0x60          */
   UNSIGNED32              GFC;                  /*!< CAN Global filter configuration,      						Address offset: 0x80          */
   UNSIGNED32              XIDAM;                /*!< CAN Extended ID and mask,        								Address offset: 0x84          */
   UNSIGNED32              HPMS;                 /*!< CAN High priority message status,         					Address offset: 0x88          */
   UNSIGNED32              RESERVED3;            /*!< reserved,       												Address offset: 0x8C          */
   UNSIGNED32              RXF0S;                /*!< CAN Rx FIFO 0 status,             							Address offset: 0x90          */
   UNSIGNED32              RXF0A;                /*!< CAN Rx FIFO 0 acknowledge,         							Address offset: 0x94          */
   UNSIGNED32              RXF1S;                /*!< CAN Rx FIFO 1 status,         								Address offset: 0x98          */
   UNSIGNED32              RXF1A;                /*!< CAN Rx FIFO 1 acknowledge,         							Address offset: 0x9C          */
   UNSIGNED32              RESERVED4[8];         /*!< reserved,         											Address offset: 0xa0          */
   UNSIGNED32              TXBC;                 /*!< CAN Tx buffer configuration,           						Address offset: 0xC0          */
   UNSIGNED32              TXFQS;                /*!< CAN Tx FIFO/queue status,             						Address offset: 0xC4          */
   UNSIGNED32              TXBRP;                /*!< CAN Tx buffer request pending,          						Address offset: 0xC8          */
   UNSIGNED32              TXBAR;                /*!< CAN Tx buffer add request,        							Address offset: 0xCC          */
   UNSIGNED32              TXBCR;                /*!< CAN Tx buffer cancellation request,         					Address offset: 0xD0          */
   UNSIGNED32              TXBTO;                /*!< CAN Tx buffer transmission occurred,         					Address offset: 0xD4          */
   UNSIGNED32              TXBCF;                /*!< CAN Tx buffer cancellation finished,       					Address offset: 0xD8          */
   UNSIGNED32              TXBTIE;               /*!< CAN Tx buffer transmission interrupt enable,           		Address offset: 0xDC          */
   UNSIGNED32              TXBCIE;               /*!< CAN Tx buffer cancellation finished interrupt enable,			Address offset: 0xE0          */
   UNSIGNED32              TXEFS;                /*!< CAN Tx event FIFO status,        								Address offset: 0xE4          */
   UNSIGNED32              TXEFA;                /*!< CAN Tx event FIFO acknowledge,         						Address offset: 0xE8          */
   UNSIGNED32              RESERVED5[5];         /*!< reserved,         											Address offset: 0xEC          */
   UNSIGNED32              CKDIV;                /*!< FD Clock divider,					         					Address offset: 0x100         */
} CODRV_MCANFD_T;

# else /* defined(CODRV_MCAN_STM32_L5) || defined(CODRV_MCAN_STM32_G0) || defined(CODRV_MCAN_STM32_G4) || defined(CODRV_MCAN_STM32_U5) */

typedef struct
{
   UNSIGNED32              CREL;                 /*!< CAN master control register,         							Address offset: 0x00          */
   UNSIGNED32              ENDN;                 /*!< CAN master status register,          							Address offset: 0x04          */
   UNSIGNED32              CUST;                 /*!< CAN transmit status register,        							Address offset: 0x08          */
   UNSIGNED32              DBTP;                 /*!< CAN Data bit timing and prescaler,							Address offset: 0x0C          */
   UNSIGNED32              TEST;                 /*!< CAN Test register,         									Address offset: 0x10          */
   UNSIGNED32              RWD;                  /*!< CAN interrupt enable register,       							Address offset: 0x14          */
   UNSIGNED32              CCCR;                 /*!< CAN CC control,           									Address offset: 0x18          */
   UNSIGNED32              NBTP;                 /*!< CAN Nominal bit timing and prescaler,							Address offset: 0x1C          */
   UNSIGNED32              TSCC;                 /*!< CAN Timestamp counter configuration,  						Address offset: 0x20          */
   UNSIGNED32              TSCV;                 /*!< CAN Timestamp counter value,          						Address offset: 0x24          */
   UNSIGNED32              TOCC;                 /*!< CAN Timeout counter configuration,    						Address offset: 0x28          */
   UNSIGNED32              TOCV;                 /*!< CAN Timeout counter value,         							Address offset: 0x2C          */
   UNSIGNED32              RESERVED0[4];         /*!< reserved,         											Address offset: 0x30          */
   UNSIGNED32              ECR;                  /*!< CAN Error counter,       										Address offset: 0x40          */
   UNSIGNED32              PSR;                  /*!< CAN Protocol status,           								Address offset: 0x44          */
   UNSIGNED32              TDCR;                 /*!< CAN Transmitter delay compensator,    						Address offset: 0x48          */
   UNSIGNED32              RESERVED1;            /*!< reserved,         											Address offset: 0x4C          */
   UNSIGNED32              IR;                   /*!< CAN Interrupt,          										Address offset: 0x50          */
   UNSIGNED32              IE;                   /*!< CAN Interrupt enable,        									Address offset: 0x54          */
   UNSIGNED32              ILS;                  /*!< CAN Interrupt line select,         							Address offset: 0x58          */
   UNSIGNED32              ILE;                  /*!< CAN Interrupt line enable,         							Address offset: 0x5C          */
   UNSIGNED32              RESERVED2[8];         /*!< reserved,       												Address offset: 0x60          */
   UNSIGNED32              GFC;                  /*!< CAN Global filter configuration,      						Address offset: 0x80          */
   UNSIGNED32              SIDFC;                /*!< CAN Standard ID filter configuration,							Address offset: 0x84          */
   UNSIGNED32              XIDFC;                /*!< CAN Extended ID filter configuration,     					Address offset: 0x88          */
   UNSIGNED32              RESERVED3;            /*!< reserved,          											Address offset: 0x8C          */
   UNSIGNED32              XIDAM;                /*!< CAN Extended ID and mask,        								Address offset: 0x90          */
   UNSIGNED32              HPMS;                 /*!< CAN High priority message status,         					Address offset: 0x94          */
   UNSIGNED32              NDAT1;                /*!< CAN New data 1,         										Address offset: 0x98          */
   UNSIGNED32              NDAT2;                /*!< CAN New data 2,       										Address offset: 0x9C          */
   UNSIGNED32              RXF0C;                /*!< CAN Rx FIFO 0 configuration,           						Address offset: 0xA0          */
   UNSIGNED32              RXF0S;                /*!< CAN Rx FIFO 0 status,             							Address offset: 0xA4          */
   UNSIGNED32              RXF0A;                /*!< CAN Rx FIFO 0 acknowledge,         							Address offset: 0xA8          */
   UNSIGNED32              RXBC;                 /*!< CAN Rx buffer configuration,          						Address offset: 0xAC          */
   UNSIGNED32              RXF1C;                /*!< CAN Rx FIFO 1 configuration,        							Address offset: 0xB0          */
   UNSIGNED32              RXF1S;                /*!< CAN Rx FIFO 1 status,         								Address offset: 0xB4          */
   UNSIGNED32              RXF1A;                /*!< CAN Rx FIFO 1 acknowledge,         							Address offset: 0xB8          */
   UNSIGNED32              RXESC;                /*!< CAN Rx buffer and FIFO element size configuration,       		Address offset: 0xBC          */
   UNSIGNED32              TXBC;                 /*!< CAN Tx buffer configuration,           						Address offset: 0xC0          */
   UNSIGNED32              TXFQS;                /*!< CAN Tx FIFO/queue status,             						Address offset: 0xC4          */
   UNSIGNED32              TXESC;                /*!< CAN Tx buffer element size configuration,         			Address offset: 0xC8          */
   UNSIGNED32              TXBRP;                /*!< CAN Tx buffer request pending,          						Address offset: 0xCC          */
   UNSIGNED32              TXBAR;                /*!< CAN Tx buffer add request,        							Address offset: 0xD0          */
   UNSIGNED32              TXBCR;                /*!< CAN Tx buffer cancellation request,         					Address offset: 0xD4          */
   UNSIGNED32              TXBTO;                /*!< CAN Tx buffer transmission occurred,         					Address offset: 0xD8          */
   UNSIGNED32              TXBCF;                /*!< CAN Tx buffer cancellation finished,       					Address offset: 0xDC          */
   UNSIGNED32              TXBTIE;               /*!< CAN Tx buffer transmission interrupt enable,           		Address offset: 0xE0          */
   UNSIGNED32              TXBCIE;               /*!< CAN Tx buffer cancellation finished interrupt enable,         Address offset: 0xE4          */
   UNSIGNED32              RESERVED4[2];         /*!< reserved,         											Address offset: 0xE8          */
   UNSIGNED32              TXEFC;                /*!< CAN Tx event FIFO configuration,          					Address offset: 0xF0          */
   UNSIGNED32              TXEFS;                /*!< CAN Tx event FIFO status,        								Address offset: 0xF4          */
   UNSIGNED32              TXEFA;                /*!< CAN Tx event FIFO acknowledge,         						Address offset: 0xF8          */
   UNSIGNED32              RESERVED5;            /*!< reserved,					         							Address offset: 0xFC          */
} CODRV_MCANFD_T;

# endif /* defined(CODRV_MCAN_STM32_L5) || defined(CODRV_MCAN_STM32_G0) || defined(CODRV_MCAN_STM32_G4) || defined(CODRV_MCAN_STM32_U5) */
#endif /* defined(CODRV_MCAN_STM32_MP1) */


/* global prototypes, that not in co_drv.h */
void codrvCanReceiveInterrupt(CO_LINE_DECL);
RET_T codrvCanTransmitInterrupt(CO_LINE_DECL);
void codrvCanErrorInterrupt(CO_LINE_DECL);

/* extern required functions */
extern void codrvCanSetTxInterrupt(CO_LINE_DECL);

#endif /* CODRV_MCAN_H */
